The present invention will be described with an example application for an Ethernet computer network peripheral device which couples a host computer system to a network of computers. In this example application, a CPU of the host computer system and the Ethernet computer network peripheral device share access to a shared memory within the host computer system. However, from this example application, it should be appreciated by one of ordinary skill in the art of electronic systems design how the present invention may be used for other applications requiring coordination of access to a shared resource by more than one electronic device.
Referring to FIG. 1, a network of computers 100 includes a first computer 102, a second computer 104, a third computer 106, and a fourth computer 108 interconnected to each other via a linking network 110. A computer peripheral device 112 is within the first computer 102 to provide added functionality to the first computer 102. For example, this computer peripheral device 112 may be an Ethernet computer network peripheral device which allows the first computer 102 to communicate with the other computers 104, 106, and 108 via the linking network 110 which may be part of the Internet.
Referring to FIG. 2, such a computer peripheral device 112 within the first computer 102 receives and transmits data packets on a network of computers 202 which includes the linking network 110, the second computer 104, the third computer 106, and the fourth computer 108 in FIG. 1. The computer peripheral device 112 which may be an Ethernet computer network peripheral device receives and transmits data packets on the network of computers 202 in accordance with standard data communications protocols such as the IEEE 802.3 network standard or the DIX Ethernet standard as is commonly known to one of ordinary skill in the art of Ethernet computer network peripheral device design.
The first computer 102 may be a PC or a workstation, and the host system of the first computer 102 includes a CPU 204 and a shared memory 206 which may be any data storage device found in a PC or a workstation. The CPU 204 further processes a data packet received from the network of computers 202 or generates a data packet to be transmitted on the network of computers 202. The shared memory 206 is shared between the CPU and the computer network peripheral device 112. In a DMA (Direct Memory Access) mode of operation, the computer network peripheral device 112 has direct access to the shared memory 206 within the host system of the first computer 102.
When the computer network peripheral device receives a data packet from the network of computers 202, that data packet is written into the shared memory 206 directly by the computer network peripheral device 112 for further processing by the host system CPU 204. The CPU 204 also accesses the shared memory 206 to further process the data packet stored within the shared memory 206.
Alternatively, the CPU 204 accesses the shared memory 206 to write a data packet to be transmitted on the network of computers 202. The computer network peripheral device 112 then accesses the shared memory 206 to read the stored data packet in order to transmit such a data packet over the network of computers 202.
Since both the CPU 204 and the computer network peripheral device 112 access the shared memory 206, a mechanism that coordinates access to the shared memory 206 between a first device (i. e. the CPU 204) and a second device (i.e. the computer network peripheral device 112) assures harmonious interaction between the two devices. For example, if the CPU 204 writes a data packet into the shared memory, the computer network peripheral device 112 for harmonious interaction reads that data packet after the CPU has sufficiently written that data packet into the shared memory 206 (i.e. when that data packet within the shared memory 206 is ready for processing by the computer network peripheral device 112). Alternatively, if the computer network peripheral device 112 receives a data packet from the network of computers 202, the computer network peripheral device 112 for harmonious interaction writes that data packet to an available space in the shared memory 206 that does not already have prior data that needs further processing.